The present invention relates to semiconductor memory devices, and more particularly, to flash memory devices that reduce read errors due to leakage current.
In general, semiconductor memory devices are classified into volatile or non-volatile memory devices depending on whether data is retained when the power is turned off. The non-volatile memory device is a memory device that can retain data even after the supply of power is stopped. In recent years, the flash memory device has been in the spotlight. Flash memory can be classified into a NOR or a NAND type memory device. The NAND flash memory device employs read and program methods on a page basis.
The flash memory device includes a memory cell array having a plurality of memory cell strings. The plurality of memory cell strings are connected to a plurality of page buffers through bit lines.
FIG. 1 is a circuit diagram of a conventional flash memory device. Referring to FIG. 1, a memory cell string 10 includes a plurality of memory cells F1 to Fi. A page buffer 20 includes a precharge control element P1, a reset element N1, a bit line select control element N2, a program control element N3, a data output control element N8, a latch circuit 30, a sensing control circuit 40, and a data input control circuit 50.
The read operation of the flash memory device shown in FIG. 1 will be described with reference to FIG. 2. If a reset signal RST is enabled at t1 of FIG. 2, the output signal QA of the page buffer 20 is reset low. If a bit line selection signal BSL is applied with a voltage of V1 (with V1≦Vcc) and a precharge signal PREb is enabled low at t2 of FIG. 2, a bit line BL is precharged to a voltage V1-Vt. If the bit line selection signal BSL is disabled to 0V at t3 of FIG. 2, the bit line BL begins discharging through the leakage current path of the memory cells F1 to Fi and the bit line BL.
In this case, if the selected memory cell is an erased cell, the voltage on the bit line BL is discharged through a selected memory cell string current (Icell) path and a bit line leakage current (Ileak) path. On the other hand, if the memory cell is a programmed cell, the voltage on the bit line BL is discharged through the leakage current (Ileak) path of the bit line BL itself. Furthermore, the leakage current Ileak of the bit line BL is a current flowing through the string of a non-selected block or a junction. As the number of blocks connected to the bit line BL is increased and the temperature rises, the leakage current Ileak of the bit line BL is increased.
If the bit line selection signal BSL is enabled to V2 at t4 of FIG. 2, the voltage of the sensing node SO is discharged through the bit line BL when the voltage passed to the bit line BL is lower than V2-Vt. Accordingly, the output signal QA is kept to an initial value “0” even though the latch control signal LAT is enabled.
Meanwhile, when the voltage applied to the bit line BL is higher than V2-Vt, the voltage of the sensing node SO is not discharged, but is kept at Vcc. Therefore, if the latch signal LAT is enabled, the output signal QA is changed from the initial value “0” to “1”.
For a programmed cell, the voltage difference between V1 and V2 must be set such that the voltage applied to the bit line BL is greater than the amount discharged by the leakage current Icell of the cell string. In addition, the voltage difference between V1 and V2 must be set such that when a memory cell is an erased cell, the voltage applied to the bit line BL is smaller than the amount discharged by the cell string current Icell.
When a selected memory cell is a programmed cell, the voltage applied to the bit line BL must be set greater than the amount discharged by the leakage current Ileak. Meanwhile, when a selected memory cell is an erased cell, the voltage applied to the bit line BL must be set smaller than the amount discharged by the sum of the cell string leakage current Icell and the bit line leakage current Ileak. The above relationship can be expressed in the following Equation 1.(Icell+Ileak)×Cp/Td>V1-V2>Ileak×(Cp/Td)  [Equation 1]
where Cp is the capacitance of the bit line BL, and Td is a time (t4-t3) at which the bit line BL is discharged.
However, the bit line leakage current Ileak may range from “0” to IleakMAX (the highest value of Ileak) depending on temperature and/or process variation. Accordingly, when considering all parameters, Equation 1 can be expressed in the following Equation 2.Icell×(Cp/Td)>V1-V2>IleakMAX×(Cp/Td)  [Equation 2]
Therefore, when the bit line leakage current Ileak is higher than the leakage current Icell of the cell string, the sensing margin is significantly reduced.
FIGS. 3a and 3b are timing diagrams illustrating variation in the voltage of the bit line depending on the amount of the bit line leakage current during the read operation of the conventional flash memory device. As shown in FIG. 3a, the bit line voltage of the erased cell is set so that it is discharged to the voltage V1-Vt or less. When the selected cell is a programmed cell and the bit line current is low, the bit line voltage is higher than V2-Vt at the time of the read operation, as indicated by the curve A1. When the selected cell is an erased cell, the bit line voltage is lower than V2-Vt as indicated by the curve C1.
However, if the bit line leakage current is increased, the bit line voltage of the program cell may become lower than V2-Vt (refer to a curve A2) as shown in FIG. 3b. In other words, a problem occurs because the selected cell can be read as an erased cell due to the leakage current although the selected cell is a programmed cell.